Quoted By: >>100197524 >>100197595 >>100198141
Why is verilog so pozzed?
WTF am I doing wrong ?
WTF am I doing wrong ?
module fsm(Mplier,Mcand,Product,clk,reset,LOAD);
input[7:0] Mplier;
input[7:0] Mcand;
output [15:0] Product;
input LOAD;
input wire clk;
input wire reset;
//////////////////////////////////////////////////
localparam S0 =3'd0,
S1 = 3'd1,
S2 =3'd2,
S3 = 3'd3,
S4 =3'd4;
///////////////////////////////////////////////
reg[1:0] Shf;
reg[1:0] K;
reg[1:0] M;
reg[3:0] CNTR;
reg[16:0] ACC;
reg[2:0] NS;
reg[2:0] PS;
assign Product[15:0] =ACC[15:0];
always@(posedge clk) begin
if(reset) PS<=S0;
else PS<=NS;
end
always@(*) begin
case(PS)
S0:begin
ACC[7:0]=Mplier;
ACC[16:8]=0;
M=ACC[0];
K=0;
CNTR=0;
Shf=0;
if(LOAD==1) NS=S1;
else NS=S0;
end
S1: begin
M=ACC[0];
if(M==1) NS=S2;
else if (M==0 & K==0) begin
ACC=ACC>>1;
CNTR=CNTR+1;
NS=S1;
if(CNTR==6) K=1;
NS=S3;
end
else if(K==1 & M==0) NS=S4;
end
S2: begin
ACC[16:8]=ACC[16:8]+Mcand[7:0];
ACC=ACC>>1;
CNTR=CNTR+1;
if(K==1) NS=S3;
else NS=S1;
end
S3: begin
ACC=ACC>>1;
CNTR=CNTR+1;
NS=S1;
end
S4: begin
ACC=ACC>>1;
end
endcase
end
endmodule
